This invention relates to a cache control technology of a storage device.
A cache memory is disposed inside a storage device so that an access from the second and on to the same data can be read out from the cache memory and a high speed access can be made.
Since the capacity of the cache memory is smaller than that of a disk device, however, it is difficult to arrange all the data in the cache memory. Therefore, the data to be arranged on the cache memory must be selected.
According to the prior art technology described in JP-A-2003-330792, the data to be stored in the cache memory are divided into those having high frequency of use and those having low frequency of use, the use area of the cache area is divided correspondingly and an upper limit size is set to each use area to prevent the data having high use frequency from being purged out by the data having low use frequency and to improve a cache hit ratio.